A high voltage detector is disclosed, which can be normally operated even if power supply voltage applied to an integrated circuit requiring high voltage is decreased.
Generally, a high voltage Vpp represents a pumped voltage, which is higher than an internal voltage driving an integrated circuit. High voltage detectors capable of detecting if the high voltage Vpp has decreased below a predetermined voltage level are commonly used in semiconductor devices.
A cell in a dynamic random access memory (DRAM) includes an NMOS transistor and a capacitor. When voltage is applied to the wordlines of the DRAM, voltage is lost due to the NMOS transistor. Accordingly, a high voltage Vpp is used as a voltage signal applied to wordlines of the cell in the DRAM. In particular, the high voltage Vpp level should be higher than the power supply voltage level.
FIG. 1 is a circuit diagram showing a high voltage detecting circuit according to the prior art. The high voltage detection circuit, which is configured to be a current mirror, includes a high voltage detecting unit 10 and a signal output unit 20. The high voltage detecting unit 10 compares the high voltage Vpp with a core voltage CVdd of a memory and generates an output signal of a predetermined potential level. The signal output unit 20 receives the output signal from the high voltage detecting unit 10 and outputs a signal of a logic xe2x80x98highxe2x80x99 or xe2x80x98lowxe2x80x99 level.
The high voltage is applied to a source of a first PMOS T1 and the core voltage of the memory is applied to a source of a second PMOS transistor T2. Because the high voltage detecting unit 10 is configured to be a current mirror, a current flowing through the first PMOS transistor T1 and a first NMOS transistor T3 is identical to a current flowing through the second PMOS transistor T2 and a second NMOS transistor T4.
If the high voltage Vpp is decreased, the current flowing through the first PMOS transistor T1 and the first NMOS transistor T3 decreases and the current flowing the second PMOS transistor T2 and the second NMOS transistor T4 is likewise decreased. Because gates of the first and second PMOS transistors T1 and T2 are connected to a ground voltage level, resistance between the source and the drain is very low so that a potential level of the drain of the first NMOS transistor T3 is increased. When the potential level of the drain of the first NMOS transistor T3 is increased to a predetermined level, a first inverter 21 in the signal output unit 20 recognizes the increased potential level as a logic xe2x80x98highxe2x80x99 level so that the first inverter 21 outputs a signal of a logic xe2x80x98lowxe2x80x99 level and the signal outputted from the first inverter 21 is inverted to a signal of logic xe2x80x98highxe2x80x99 level by a second inverter to create a pumping signal Vppen.
Because the high voltage detecting circuit using the current mirror compares the high voltage Vpp with the core voltage CVdd of the memory, when power supply voltage level is decreased, the high voltage detecting circuit can not detect whether the high voltage Vpp and the core voltage CVdd of the memory are simultaneously decreased. For example, when the power supply voltage is decreased from 3.3V to 2.5V, because the high voltage Vpp and the core voltage CVdd of the memory are simultaneously decreased at a uniform rate, the pumping signal Vppen, which is used for pumping the high voltage Vpp, is not enabled. Accordingly, there is a problem because the conventional high voltage detecting circuit cannot properly operate when the power supply voltage is changed.
The disclosed apparatus may be a high voltage detector used in an integrated circuit having a high voltage generator for generating high voltage boosting internal voltage. Such an apparatus may include a reference voltage supplying unit for supplying reference voltage and a low voltage detecting unit for comparing the reference voltage and the internal voltage and generating a low voltage detecting signal, which is enabled when the internal voltage level is less than a predetermined voltage level. The apparatus may further include a control signal outputting unit, which is configured as a current mirror and to which the high voltage and the internal voltage are applied, for controlling current flowing through the current mirror in response to the low voltage detecting signal and outputting a pumping control signal having a first or a second potential level.